Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra

TUNA M., FİDAN C. B. , Koyuncu I., PEHLİVAN İ.

24th Signal Processing and Communication Application Conference (SIU), Zonguldak, Türkiye, 16 - 19 Mayıs 2016, ss.1309-1312 identifier identifier

  • Cilt numarası:
  • Doi Numarası: 10.1109/siu.2016.7495988
  • Basıldığı Şehir: Zonguldak
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.1309-1312


In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.